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Symbolator

Symbolator creates a component symbol from a hardware module declaration.

Use this type​

Use Symbolator to document component ports, directions, groups, and data widths.

Source format​

The source format is VHDL or Verilog source. Enter the source in the diagram.zip editor.

Syntax essentials​

  • Declare a VHDL entity or a Verilog module.
  • Declare the ports that must appear in the symbol.
  • Use supported comments to group ports.
  • Select the component when the source has more than one.

Example​

module diagram (
  input wire clock,
  input wire data_in,
  output wire data_out
);
endmodule
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Upstream reference​

Symbolator documentation